Synchronous dynamic random-access memory (SDRAM) is any dynamic random-access memory (DRAM) where the operation of its external pin interface is coordinated by an externally supplied clock signal. DRAM integrated circuits (ICs), between the mid-1970s and -1990s typically had an asynchronous interface, where responses to changes in control signal inputs occur as soon as they are received. SDRAM has a synchronous interface, meaning that a clock signal must be received before it responds to the control inputs. The interfaces of SDRAM ICs is therefore synchronous to the clock signal used. In the family of devices standardized by JEDEC, which are called synchronous DRAMs (SDRAMs), the clock signal is used to drive an internal finite state machine that pipelines incoming commands. The memory is divided into several independent sections of memory called banks, allowing the device to operate on several memory access commands at a time, provided the commands are independent of each other (in an interleaved fashion). This allows SDRAMs to achieve greater concurrency and higher data transfer rates than asynchronous DRAMs.