In
integrated circuit design,
dynamic logic (or sometimes
clocked logic) is a design methodology in
combinatory logic circuits, particularly those implemented in
MOS technology. It is distinguished from the so-called static logic by exploiting temporary storage of information in stray and gate capacitances. It was popular in the 1970s and has seen a recent resurgence in the design of high speed digital
electronics, particularly
computer CPUs. Dynamic logic circuits are usually faster than static counterparts, and require less surface area, but are more difficult to design. Dynamic logic has a higher toggle rate than static logic but the capacitative loads being toggled are smaller so the overall power consumption of dynamic logic may be higher or lower depending on various tradeoffs. When referring to a particular
logic family, the dynamic adjective usually suffices to distinguish the design methodology, e.g.
dynamic CMOS or
dynamic SOI design.